1. Field of the Invention
The present invention relates to a thin film transistor and more particularly, to the structure of a thin film transistor which guarantees a stable off-set region. The present invention is also directed to the method of fabricating the thin film transistor.
2. Discussion of Related Art
In general, a thin film transistor (TFT) is used for an SRAM device having over 1M bites of storage capacity, instead of a PMOS load transistor or a load resister, and is also widely used in a switching device for switching an image data signal of each image region in a liquid crystal display. Specifically, if an off current of the PMOS transistor is reduced and its on current is increased in the SRAM cell employing the PMOS TFT as the load transistor, the consumed power of the SRAM cell is decreased and its memory characteristic is enhanced, thereby producing a high quality SRAM cell. Therefore, research on enhancing the on/off current ratio has been actively progressed in recent years.
With reference to the attached drawings, the fabricating procedures of a conventional TFT for enhancing its on/off current ratio will be described below.
As illustrated in FIGS. 1a through 1d, the conventional TFT is fabricated to have a large-sized grain using a solid phase epitaxy (SPE) method of a polysilicon body on the basis of a bottom gate. The SPE method performs a heat treatment at 600.degree. C. for 24 hours. That is, as illustrated in FIG. 1a, polysilicon is deposited on an insulating substrate 1 or insulating layer or silicon substrate, and patterned by photolithography using a gate mask, thereby forming a gate electrode 2. As illustrated in FIG. 1b, a gate oxide layer 3 is deposited over the surface of the substrate by chemical vapor deposition (CVD) or by thermal oxidation. A polysilicon body layer 4 is successively deposited on the gate oxide layer 3 by CVD. Then the SPE method is performed at 600.degree. C. for 24 hours to enlarge the size of the polysilicon body grain 4. As illustrated in FIG. 1c, a photoresist layer 5 is deposited on the polysilicon body layer 4 and its channel region is masked by an exposing and developing process. Here, the channel is masked in a manner such that the source region 6a overlaps with the gate electrode 2, and the drain region 6b is off-set with respect to the gate electrode 2. As illustrated in FIG. 1d, a P-type ion impurity, namely, a boron ion is implanted in the exposed polysilicon body layer 4 in the case of the PMOS transistor, and an N-type impurity ion, namely, phosphorus ion or Arsenic ion is implanted thereinto in the case of the NMOS transistor to form a source/drain region. In FIG. 1d, reference character "a" is the source region, reference character "b" is a channel region, reference character "c" is the off set region, and reference character "d" is the drain region.
However, the thus-structured conventional TFT has the following problems:
First, as the photo mask process defines the channel region together with the off set region, it is too complicated to implement the process. In addition, since the variation of the off current is serious, according to the alignment, the reliability of the TFT is decreased.
Second, since the length of the channel off set region of the TFT affects the cell's size, it causes difficulty in integration.